Not applicable.
This invention relates generally to integrated circuits, and more particularly, to analog to digital converters.
As is known in the art, analog-to-digital converters (ADCs) convert a signal in analog format to a signal in digital format. Conventional ADC circuits can have a variety of circuit architectures each of which has certain concomitant disadvantages. Known ADC architectures include pipeline, sigma-delta, cyclic, flash, successive approximation, and dual-slope. Each architecture is generally applicable to a limited operating range. That is, each of these architectures has strengths and weaknesses that make them more amenable to working in certain frequency and resolution ranges.
Some ADC architectures do not operate outside certain ranges or consume prohibitively high power in certain ranges as compared to other architectures. Even within preferred operating ranges, a given architecture can have a performance level that is dictated by certain circuit parameters that are fixed for a given design. For example, ADCs generally include op amps that operate at a speed dictated by the bandwidth required of them. To operate at different speeds, the op amp bandwidth must be altered in an efficient way. Likewise, the resolution of certain ADC architectures is fixed by the thermal noise contribution of the components within it and hence varies with the circuit design.
There have been various attempts to create digitization systems having a relatively wide operating range. One such method includes employing a single very high-performance ADC that can work at the highest common denominator of resolution and sampling rate. However, this strategy is not practical and is extremely power inefficient.
An alternate approach employs multiple A/D converter architectures each covering a small sector in the overall two-dimensional space. This implementation, however, requires a prohibitively large number of ADCs to achieve optimal power consumption with a reasonably fine granularity over input bandwidth and resolution. For example, the fraction of the application space bounded by data-rate and resolution ranging between 20 Hz-20 Khz and 8-18 bits, respectively; in order for the system to achieve a power consumption that in the worst case is as much as a factor four times the optimal levelxe2x80x94would require the system to include 50 different converters working in tandem. This does not even consider a higher portion of the bandwidth spectrum. In a discrete chip implementation, there would be a tremendous power overhead merely due to vast amounts of PCB wiring to connect the various architectures.
U.S. Pat. No. 5,691,720 entitled xe2x80x9cDelta sigma analog-to-digital converter having programmable resolution/bias current circuitry and methodxe2x80x9d provides variable resolution in a delta-sigma type ADC by controlling the Oversampling Ratio (OSR) of the ADC over certain fixed values. In order to make the opamps settle faster (because of the varying clock frequency), the bias current is varied over values that are predetermined for the each of the different oversampling ratios. This fixed arrangement offers relatively limited resolution reconfigurability at lower bandwidths. In addition, relying upon a predetermined bias current for each oversampling ratio works only if the relationship of speed of the operational amplifiers versus its bias current is fixed. However, this relationship does not hold over different fabrication processes. Even within the same process, it is not possible to know this relationship (especially since bias current variation would place the input devices of the opamps into different regimes) in advance of building the chip. While it is possible to make a calibration run for a given process and chip, this adds significant cost.
In another prior art attempt, Texas Instruments of Dallas, Tex., manufactures an ADC having part number TLV1562. Currently, this ADC operates only at the following selected values: 10 bit/3 Msps, 8 bit/4 Msps and 4 bit/8 Msps. Thus, this ADC offers limited reconfigurability.
U.S. Pat. No. 5,877,720 entitled xe2x80x9cReconfigurable analog-to-digital converterxe2x80x9d discloses a flash ADC having a limited reconfigurability, i.e., 2 settings: 5.75 b 350 Msample/s or 6.75b 150 Msample/s.
Yet another approach is described in xe2x80x9cA CMOS Programmable Self-Calibrating 13-bit Eight Channel Data Acquisition Peripheral,xe2x80x9d Ohara et. al., Journal of Solid-State Circuits, December 1989. This article describes an ADC having resolution reconfigurability with a single cyclic ADC that can be configured for 8, 13, or 16 cycles. It should be noted that this architecture can work at 16 bits only with elaborate digital calibration.
It would, therefore, be desirable to provide a reconfigurable ADC that overcomes the aforesaid and other disadvantages.
The present invention provides an ADC circuit having a series of circuit blocks that can be reconfigured for a selected architecture to optimize the ADC for a particular resolution and data rate. This arrangement provides an ADC that can cover a relatively large resolution and data rate space with minimum power consumption at each performance level.
In one aspect of the invention, a reconfigurable ADC in accordance with the present invention is architecturally configurable such that the ADC can be configured in a selected one of a plurality of architectures. The reconfigurable ADC includes a plurality of reconfigurable blocks each having a capacitor array and at least one switch array and reconfiguration interface circuitry. The arrays provide a digitized signal to an interface circuit and a processed analog signal to the next reconfigurable block. The capacitor array and switch arrays are configured to provide a selected ADC architecture. In one embodiment, the ADC can be configured to operate in a pipeline mode and a sigma-delta mode.
In a further aspect of the invention, a phase-locked loop (PLL) circuit provides optimal bias current signal to the ADC opamps based upon an input clock signal and the desired resolution. In one embodiment, the PLL circuit includes a phase-frequency detector that provides an output signal proportional to a frequency difference between the input clock signal and an oscillation frequency of a voltage controlled oscillator. The frequency difference output signal is integrated using a charge pump and its output presented to a voltage-to-current converter circuit that provides an optimal bias current signal to the ADC opamps. Thus, the PLL circuit provides bandwidth reconfigurability.
In one embodiment, the voltage controlled oscillator includes a series of opamps having substantially similar characteristics to those of the opamps in the ADC. With this arrangement, the oscillation frequency of the voltage controlled oscillator is proportional to the speed of the opamps, which is non-linearly proportional to the opamp bias current. The voltage controlled oscillator frequency tracks the clock input signal frequency such that an increase in the clock input signal frequency, i.e., a higher sampling frequency, causes a concomitant increase in the opamp bias current. Thus, the speed of the opamps is linearly proportional to the input clock signal frequency.
In a further aspect of the invention, the ADC is parametrically configurable for power optimization in relation to the selected resolution. In one embodiment, the capacitors in the reconfigurable blocks are scaled from block to block. In an exemplary embodiment having eight reconfigurable blocks, the second reconfigurable block can have capacitors that are one-fourth the size of the capacitors in the first block, for example. In addition, the particular blocks enabled for a given resolution can be selected based upon the size of the capacitors in the respective blocks.
A reconfigurable ADC in accordance with the present invention can digitize a relatively wide range of input bandwidth and provide a relatively wide resolution range while maintaining optimal power performance through the input-bandwidth/resolution space. In one embodiment, the input bandwidth is in the range of about 1 Mhz to about 20 Mhz and the resolution is in the range of about 2 bits to about 18 bits.